1. Field of the Invention
The present invention relates to a semiconductor device comprising a redundancy circuit for relieving a failed data line.
2. Description of the Related Art
There have been redundancy systems in semiconductor memory devices such as DRAMs to replace a failed cell with a redundancy cell as known in the art. A conventional common fixed data shift redundancy system comprises DQ buffer blocks operative to amplify data and fixed data shift redundancy circuit blocks in each relief target memory block. Namely, the ability of a fixed data shift redundancy circuit block is limited to relieve only one memory block (one relief area) (Patent Document 1: JP 2004-118920A).
Expansion of submacros in the conventional system requires the DQ buffer block and the fixed data shift redundancy circuit block to be arranged in each relief area, which presses the chip area. A reduction in the number of DQ buffer blocks inside the DRAM for the purpose of reducing the area increases the relief areas and lowers the relief efficiency as a problem.